(Click Category to List Courses)

18 - EEE - Electrical & Electronics Engineering

EEE 181 - Expert VHDL

Code Start Date Duration Venue
EEE 181 10 April 2023 5 Days Istanbul Registration Form Link
EEE 181 05 June 2023 5 Days Istanbul Registration Form Link
EEE 181 31 July 2023 5 Days Istanbul Registration Form Link
EEE 181 25 September 2023 5 Days Istanbul Registration Form Link
EEE 181 20 November 2023 5 Days Istanbul Registration Form Link
EEE 181 18 December 2023 5 Days Istanbul Registration Form Link
Please contact us for fees


Course Description

Expert VHDL is an intensive 5-day advanced application class. It teaches engineers how to increase Learning Pathproductivity by enhancing their knowledge of the VHDL language itself and its application for design and verification. Presented in two distinct course modules, Expert VHDL focuses on language and synthesis issues, design maintainability and re-use, structured verification environments and the latest techniques for verification - including an introduction to OVL/PSL and introductions to OSVVM and UVVM.

The minumum number of participants for this course is 5.

Course Objectives

  • A set of VHDL language features that go beyond what is taught on a basic training class
  • Having a deeper understanding of how to apply VHDL language for design
  • Enabling participants to troubleshoot VHDL simulation and synthesis problems with ease
  • Enabling code re-use
  • Understanding the principles and details of how to approach the problem of design verification using VHDL
  • Learning how to structure and write large and complex VHDL structured verification environments
  • Discussing the OSVVM and UVVM VHDL verification methodologies

Who Should Attend?

  • Design engineers wishing to improve the efficiency of their hardware designs and increase productivity
  • Design and verification engineers who want to structure and write effective test environments to verify complex designs and systems

Course Details/Schedule

Day 1

  • RTL Synthesis & Synchronisation
  • Readable Designs Writing For Re-use
  • Advanced Coding

Day 2

  • FSM Synthesis Packages & Configurations
  • Properties & Assertions

Day 3

  • Verification Methodology Subprograms & Protected
  • Types More on File VO
  • Transaction Level Verification

Day 4

  • Time in Testbenches Modelling & Checkars
  • Random Testing & Coverage

Day 5

  • Other Testbench Features OSVVM UVVM