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15 - EEE - Electrical & Electronics Engineering


EEE 200 - Xilinx - Vivado Adopter Class for New Users

Code Start Date Duration Venue
EEE 200 19 September 2022 5 Days Ankara Registration Form Link
EEE 200 21 November 2022 5 Days Ankara Registration Form Link
Please contact us for fees

 

Course Description

The training provides an introduction to the Vivado® Design Suite. Learn about the Vivado Design Suite projects, design flow, Xilinx design constraints and basic timing reports.

Participants will also learn about the underlying database and Static Timing Analysis (STA) mechanisms. Utilize Tcl for navigating the design, creating Xilinx Design Constraints (XDC) and creating timing reports. Learn to make appropriate timing constraints for SDR, DDR, source-synchronous, and system-synchronous interfaces for your FPGA design.

In addition, participants will learn about making path-specific, false path and min/max timing constraints, as well as timing constraint priority in the Vivado timing engine

The minumum number of participants for this course is 5.

 

Course Objectives

  • Build an effective FPGA design using synchronous design techniques
  • Understand the configuration process
  • Instantiate appropriate device resources
  • Use proper HDL coding techniques
  • Learn sophisticated aspects of the Vivado Design Suite to use its advanced capabilities to achieve design closure

Who Should Attend?

  • Digital designers who have a working knowledge of an HDL (VHDL, Verilog or SystemVerilog) but are new to Xilinx FPGAs.
  • Existing Xilinx ISE users who have little or no knowledge of 7-Series or UltraScale devices.

Course Details/Schedule

Day 1

  • Introduction to FPGA Architecture, 3D IC, SoC
  • CLB architecture
  • Clocking Resources
  • I/O Logic Resources
  • Introduction to FPGA Configuration
  • Configuration Process
  • Configuration Modes
  • Synchronous Design Techniques
  • Register Duplication
  • Pipelining

Day 2

  • Introduction to Vivado Design Flows
  • Vivado Design Suite Project Mode
  • Synthesis and Implementation
  • Basic Design Analysis in the Vivado IDE
  • Vivado Design Suite I/O Pin Planning
  • Vivado IP Flow
  • Using an IP Container
  • Designing with IP Integrator
  • Introduction to the Tcl Environment

Day 3

  • Managing Remote IP
  • Introduction to the Tcl Environment
  • Scripting in Vivado Design Suite Project Mode
  • Vivado Design Suite Non-Project Mode
  • Scripting in Vivado Design Suite Non-Project Mode
  • Design Analysis Using Tcl Commands
  • Timing Constraints Wizard
  • Timing Constraints Editor
  • Introduction to Clock Constraints
  • Report Clock Networks
  • Setup and Hold Timing Analysis
  • Introduction to Vivado Reports

Day 4

  • I/O Constraints and Virtual Clocks
  • Timing Summary Report
  • Generated Clocks
  • Clock Group Constraints
  • Introduction to Timing Exceptions
  • Synchronization Circuits
  • Report Clock Interaction
  • Timing Constraints Priority
  • Case Analysis
  • Revision Control Systems in the Vivado Design Suite
  • UltraFast Design Methodology: Planning
  • UltraFast Design Methodology: Design Creation and Analysis

Day 5

  • HDL Coding Techniques
  • Resets
  • Baselining
  • I/O Timing Scenarios
  • System-Synchronous I/O Timing
  • Source-Synchronous I/O Timing
  • Report Datasheet
  • UltraFast Design Methodology: Design Closure
  • UltraFast Design Methodology: Advanced Techniques
  • Introduction to Floorplanning
  • Introduction to floorplanning and how to use Pblocks while floorplanning
  • Physical Optimization