(Click Category to List Courses)

15 - EEE - Electrical & Electronics Engineering

EEE 201 - Xilinx - Vivado Adopter Class (4 Days)

Code Start Date Duration Venue
EEE 201 20 September 2022 4 Days Ankara Registration Form Link
EEE 201 22 November 2022 4 Days Ankara Registration Form Link
Please contact us for fees


Course Description

This training provides an introduction to the Vivado Design Suite. Learn about the Vivado Design Suite projects, design flow, Xilinx design constraints and basic timing reports.

Participants will also learn about the underlying database and Static Timing Analysis (STA) mechanisms. Utilize Tcl for navigating the design, creating Xilinx Design Constraints (XDC) and creating timing reports. Learn to make appropriate timing constraints for SDR, DDR, source-synchronous and system-synchronous interfaces for your FPGA design.

The minumum number of participants for this course is 5.

Course Objectives

  • Introduces the Vivado design flows: the project flow and non-project batch flow
  • Use the various design analysis features in the Vivado Design Suite
  • Introduces Tcl (tool command language).
  • Create a design in the Vivado Design Suite non-project mode
  • Apply I/O constraints and perform timing analysis
  • Introduces timing exception constraints and applying them to fine tune design timing
  • Use Xilinx-recommended baselining procedures to progressively meet timing closure
  • Introduces the methodology guidelines for advanced techniques

Who Should Attend?

FPGA designers looking to utilize Vivado who:

  • currently use the Xilinx ISE® Design Suite
  • already have some familiarity with Xilinx 7-Series devices

Course Details/Schedule

Day 1

  • Introduction to Vivado Design Flows
  • Vivado Design Suite Project Mode
  • Synthesis and Implementation
  • Basic Design Analysis in the Vivado IDE
  • Vivado Design Suite I/O Pin Planning
  • Vivado IP Flow
  • Using an IP Container
  • Designing with IP Integrator
  • Introduction to the Tcl Environment

Day 2

  • Managing Remote IP
  • Introduction to the Tcl Environment
  • Scripting in Vivado Design Suite Project Mode
  • Vivado Design Suite Non-Project Mode
  • Scripting in Vivado Design Suite Non-Project Mode
  • Design Analysis Using Tcl Commands
  • Timing Constraints Wizard
  • Timing Constraints Editor
  • Introduction to Clock Constraints
  • Report Clock Networks
  • Setup and Hold Timing Analysis
  • Introduction to Vivado Reports

Day 3

  • I/O Constraints and Virtual Clocks
  • Timing Summary Report
  • Generated Clocks
  • Clock Group Constraints
  • Introduction to Timing Exceptions
  • Synchronization Circuits
  • Report Clock Interaction
  • Timing Constraints Priority
  • Case Analysis
  • Revision Control Systems in the Vivado Design Suite
  • UltraFast Design Methodology: Planning
  • UltraFast Design Methodology: Design Creation and Analysis

Day 4

  • HDL Coding Techniques
  • Resets
  • Baselining
  • I/O Timing Scenarios
  • System-Synchronous I/O Timing
  • Source-Synchronous I/O Timing
  • Report Datasheet
  • UltraFast Design Methodology: Design Closure
  • UltraFast Design Methodology: Advanced Techniques
  • Introduction to Floorplanning
  • Physical Optimization