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15 - EEE - Electrical & Electronics Engineering


EEE 185 - Comprehensive VHDL

Code Start Date Duration Venue Fees
EEE 185 21 June 2021 5 Days Istanbul $ 3950 Registration Form Link
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Course Description

Comprehensive VHDL is the industry standard 5-day training course teaching the application of VHDL for FPGA and ASIC design. Fully updated and restructured to reflect current best practice, engineers can attend either the individual modules, or the full 5-day course. It prepares the engineer for practical project readiness for FPGA designs. While the emphasis is on the practical VHDL-to-hardware flow for FPGA devices, this module also provides the essential foundation needed by ASIC and FPGA designers wishing to apply the more advanced features of VHDL covered in the next module. Delegates targeting FPGAs will take away a flexible project infrastructure which includes a set of scripts, example designs, modules and constraint files to use, adapt and extend on their own projects.

It builds on the foundation of the previous module to prepare the engineer for complex FPGA or ASIC design. It focuses on the use of VHDL for large hierarchical designs, design re-use, and the creation of more powerful test benches.

Course Objectives

  • Learning the VHDL language concepts and constructs essential for FPGA design
  • Understanding how to write VHDL for effective RTL synthesis
  • Learning how to target VHDL code to an FPGA device architecture
  • Discussing how to write simple VHDL test benches
  • Understaning the tool flow from VHDL through simulation, synthesis and place-and-route
  • Exploring how to write high quality VHDL code that reflects best practice in the industry 

Who Should Attend?

  • Engineers who wish to become skilled in the practical use of VHDL for FPGA or ASIC design
  • Engineers who are about to embark on the first VHDL design project
  • Engineers who have already acquired some practical experience in the use of VHDL, but wish to consolidate and extend their knowledge within a training environment

Course Details/Schedule

Day 1

  • The basic VHDL language constructs
  • FPGA Design Flow 
  • Entities and Architectures
  • The Process Statement
  • Synthesising Combinational Logic

Day 2

  • VHDL Types
  • Synthesis of Arithmetic
  • Synthesising Sequential Logic
 

Day 3

  • FSM Synthesis
  • Memories
  • Basic TEXTIO

Day 4

  • More Effective VHDL
  • Managing Hierarchical Designs
  • Parameterised Design Entities
 

Day 5

  • Procedural Testbenches
  • Text-File-Based Testbenches
  • Gate Level Simulation