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19 - EEE - Electrical & Electronics Engineering

EEE 185 - Comprehensive VHDL

Code Start Date Duration Venue
EEE 185 24 November 2024 5 Days Istanbul Registration Form Link
Please contact us for fees


Course Description

Comprehensive VHDL is the industry standard 5-day training course teaching the application of VHDL for FPGA and ASIC design. Fully updated and restructured to reflect current best practice, engineers can attend either the individual modules, or the full 5-day course. It prepares the engineer for practical project readiness for FPGA designs. While the emphasis is on the practical VHDL-to-hardware flow for FPGA devices, this module also provides the essential foundation needed by ASIC and FPGA designers wishing to apply the more advanced features of VHDL covered in the next module. Delegates targeting FPGAs will take away a flexible project infrastructure which includes a set of scripts, example designs, modules and constraint files to use, adapt and extend on their own projects.

It builds on the foundation of the previous module to prepare the engineer for complex FPGA or ASIC design. It focuses on the use of VHDL for large hierarchical designs, design re-use, and the creation of more powerful test benches.

The minumum number of participants for this course is 5.

Course Objectives

  • Understanding the VHDL language concepts and constructs essential for FPGA design
  • Learning how to write VHDL for effective RTL synthesis
  • Learning how to target VHDL code to an FPGA device architecture
  • Learning how to write simple VHDL test benches
  • Mastering the tool flow from VHDL through simulation, synthesis and place-and-route
  • Learning how to write high quality VHDL code that reflects best practice in the industry
  • Understanding the VHDL language concepts constructs essential for complex FPGA and ASIC design
  • Understanding the VHDL language constructs and coding styles that enable sophisticated test benches
  • Learning how to code hierarchical designs using multiple VHDL design libraries
  • Learning how to write re-usable, parameterisable VHDL code by exploiting generics and data types
  • Learning how to run gate-level simulations

Who Should Attend?

  • Engineers who wish to become skilled in the practical use of VHDL for FPGA or ASIC design
  • Engineers who are about to embark on the first VHDL design project
  • Engineers who have already acquired some practical experience in the use of VHDL, but wish to consolidate and extend their knowledge within a training environment

Course Details/Schedule

Day 1

  • Introduction to the scope and application of VHDL
  • Getting Started
  • FPGA Design Flow (Practical exercises using a hardware board)
  • Design Entities


Day 2

  • Processes
  • Synthesising Combinational Logic
  • VHDL types
  • Synthesis of Arithmetic

Day 3

  • Synthesising Sequential Logic
  • FSM Synthesis
  • Memories
  • Basic TEXTIO

Day 4

  • Managing Hierarchical Designs
  • Parameterised Design Entities
  • More About Types

Day 5

  • Procedural Testbenches
  • Text-File-Based Testbenches
  • Gate Level Simulation